Digital Electronics

A. OR gate
B. AND gate
C. NOT gate
D. None of the above

A. NAND gate
B. OR gate
C. AND gate
D. None of the above

A. A & B
B. C & D
C. A & D
D. B & C

A. PLCC
B. QFP
C. PGA
D. BGA

A. OR operation
B. AND operation
C. NOT operation
D. None of the above

A. Input operation
B. Tristate output operation
C. Bi-directional I/O pin access
D. All of the above

A. State Reduction
B. State Minimization
C. State Assignment
D. State Evaluation

A. OR gates
B. NOT gates
C. NAND gates
D. None of the above

A. 0
B. 1
C. Either 0 & 1
D. None of the above

A. NOT gate
B. OR gate
C. AND gate
D. None of the above